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EURODAC
1994
IEEE
139views VHDL» more  EURODAC 1994»
12 years 1 months ago
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
: This paper presents an approach to high-level synthesis which is based upon a 0/1 integer programming model. In contrast to other approaches, this model allows solving all three ...
Birger Landwehr, Peter Marwedel, Rainer Dömer
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
12 years 1 months ago
Parallel algorithms for the simulation of lossy transmission lines
The simulation of lossy transmission lines in the time domain is a very time consuming task. It requires numerical convolutions and the solution of linear and nonlinear equation s...
W. Rissiek, O. Rethmeier, H. Holzheuer
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
12 years 1 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
EURODAC
1994
IEEE
221views VHDL» more  EURODAC 1994»
12 years 1 months ago
Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools
payload. The current recommendations include SDH as the physical layer transmission standard. It is defined the BISDN user network interface (UNI) SDH-based at 155.52 Mbit/s, but t...
Juan Carlos Calderón, Enric Corominas, Jos&...
EURODAC
1994
IEEE
112views VHDL» more  EURODAC 1994»
12 years 1 months ago
The use of semantic information for control of a complex routing tool
To handle increasingly complex design data, CAD tools are becoming more specialised and complex and hence, more difficult to use. This paper describes an interactive system that h...
Michael Brown, Nick Filer, Zahir Moosa
EURODAC
1994
IEEE
128views VHDL» more  EURODAC 1994»
12 years 1 months ago
A component selection algorithm for high-performance pipelines
The use of a realistic component library with multiple implementations of operators, results in cost ef cient designs; slow components can then be used on non-critical paths and t...
Smita Bakshi, Daniel D. Gajski
EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
12 years 1 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
12 years 1 months ago
Using C to write portable CMOS VLSI module generators
Alain Greiner, Frédéric Pétro...
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
12 years 1 months ago
RESIST: a recursive test pattern generation algorithm for path delay faults
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
Karl Fuchs, Michael Pabst, Torsten Rössel
EURODAC
1994
IEEE
115views VHDL» more  EURODAC 1994»
12 years 1 months ago
Overall thermal simulation of electronic equipment
Jean-Louis Blanchard, Jean-Michel Morelle
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