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ISCA
2007
IEEE
167views Hardware» more  ISCA 2007»
10 years 9 months ago
New cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
Zhenghong Wang, Ruby B. Lee
ISCA
2007
IEEE
177views Hardware» more  ISCA 2007»
10 years 9 months ago
Adaptive insertion policies for high performance caching
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applica...
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, ...
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
10 years 9 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
IPPS
2007
IEEE
10 years 9 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
IEEEPACT
2007
IEEE
10 years 9 months ago
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Jaideep Mo...
HPCA
2007
IEEE
10 years 9 months ago
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
Haakon Dybdahl, Per Stenström
DATE
2007
IEEE
98views Hardware» more  DATE 2007»
10 years 9 months ago
A one-shot configurable-cache tuner for improved energy and performance
We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application....
Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A...
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
10 years 9 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
DASFAA
2007
IEEE
141views Database» more  DASFAA 2007»
10 years 9 months ago
CST-Trees: Cache Sensitive T-Trees
Abstract. Researchers have modified existing index structures into ones optimized for CPU cache performance in main memory database environments. A Cache Sensitive B+-Tree is one o...
Ig-hoon Lee, Junho Shim, Sang-goo Lee, Jonghoon Ch...
DASFAA
2007
IEEE
114views Database» more  DASFAA 2007»
10 years 9 months ago
A Workload-Driven Unit of Cache Replacement for Mid-Tier Database Caching
Making multi-terabyte scientific databases publicly accessible over the Internet is increasingly important in disciplines such as Biology and Astronomy. However, contention at a c...
Xiaodan Wang, Tanu Malik, Randal C. Burns, Stratos...
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