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IPPS
2005
IEEE
10 years 8 months ago
Effective Instruction Prefetching via Fetch Prestaging
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
Ayose Falcón, Alex Ramírez, Mateo Va...
IEEEPACT
2005
IEEE
10 years 8 months ago
Trace Cache Sampling Filter
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...
Michael Behar, Avi Mendelson, Avinoam Kolodny
ICPP
2005
IEEE
10 years 8 months ago
Toward Effective NIC Caching: A Hierarchical Data Cache Architecture for iSCSI Storage Servers
In this paper, we present a hierarchical Data Cache Architecture called DCA to effectively slash local interconnect traffic and thus boost the storage server performance. DCA is ...
Xiaoyu Yao, Jun Wang
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
10 years 8 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
10 years 8 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
DATE
2005
IEEE
132views Hardware» more  DATE 2005»
10 years 8 months ago
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...
ACISICIS
2005
IEEE
10 years 8 months ago
An Effective Cache Overlapping Storage Structure for SMT Processors
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
Liqiang He, Zhiyong Liu
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
10 years 8 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
STOC
2006
ACM
121views Algorithms» more  STOC 2006»
10 years 8 months ago
On adequate performance measures for paging
Memory management is a fundamental problem in computer architecture and operating systems. We consider a two-level memory system with fast, but small cache and slow, but large mai...
Konstantinos Panagiotou, Alexander Souza
ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
10 years 8 months ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob
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