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EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
11 years 3 months ago
Modeling shared variables in VHDL
A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing su...
Jan Madsen, Jens P. Brage
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
11 years 3 months ago
Distributed simulation for structural VHDL netlists
: This article describes the current state of the project to develop distributed simulation. The reader will have
David B. Bernstein, Werner van Almsick, Wilfried D...
EURODAC
1994
IEEE
133views VHDL» more  EURODAC 1994»
11 years 3 months ago
Mixed electrical-thermal and electrical-mechanical simulation of electromechatronic systems using PSpice
- The design methodology and technique is presented to expand the power of commercial SPICE to simulate mixed electricalthermal-mechanical microsystems, consisting of motors being ...
Konstantin O. Petrosjanc, Peter P. Maltcev
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
11 years 3 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
EURODAC
1994
IEEE
186views VHDL» more  EURODAC 1994»
11 years 3 months ago
Algorithms for a switch module routing problem
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
Shashidhar Thakur, D. F. Wong, S. Muthukrishnan
EURODAC
1994
IEEE
122views VHDL» more  EURODAC 1994»
11 years 3 months ago
Compiled-code-based simulation with timing verification
Due to the complexity of today's systems, prototyping by simulation must be based on simulation-engine-like performance. It is proved by implementations that compiler-driven ...
Winfried Hahn, Andreas Hagerer, C. Herrmann
EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
11 years 3 months ago
Generating compilers for generated datapaths
Modern CAD systems allow the designers to come up with powerful programmable datapaths in avery short time. The time to develop compilers for this datapaths is much longer. This p...
Michael Held, Manfred Glesner
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
11 years 3 months ago
A process algebra interpretation of a verification oriented overlanguage of VHDL
The VOVHDL language was defined as a verification oriented VHDL
Catherine Bayol, Bernard Soulas, Dominique Borrion...
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