Sciweavers

FPT
2005
IEEE
134views Hardware» more  FPT 2005»
13 years 10 months ago
Post-Silicon Debug Using Programmable Logic Cores
Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabr...
Bradley R. Quinton, Steven J. E. Wilton
GLVLSI
2006
IEEE
119views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Thermal analysis of a 3D die-stacked high-performance microprocessor
3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional plan...
Kiran Puttaswamy, Gabriel H. Loh
CIMCA
2006
IEEE
13 years 10 months ago
Computational Nanomechatronics: A Pathway for Control and Manufacturing Nanorobots
This paper describes an innovative work for nanorobot design and manufacturing, using a computer simulation and system on chip prototyping approach. The use of CMOS as integrated ...
Adriano Cavalcanti, Warren W. Wood, Luiz C. Kretly...
SLIP
2009
ACM
13 years 11 months ago
From 3D circuit technologies and data structures to interconnect prediction
New technologies such as 3D integration are becoming a new force that is keeping Moore’s law in effect in today’s nano era. By adding a third dimension in current 2D circuits...
Robert Fischbach, Jens Lienig, Tilo Meister
SLIP
2009
ACM
13 years 11 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
ASPDAC
2009
ACM
104views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Addressing thermal and power delivery bottlenecks in 3D circuits
— The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footpr...
Sachin S. Sapatnekar
ICCAD
2006
IEEE
208views Hardware» more  ICCAD 2006»
14 years 1 months ago
Automation in mixed-signal design: challenges and solutions in the wake of the nano era
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
Trent McConaghy, Georges G. E. Gielen
DAC
2002
ACM
14 years 5 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
DAC
2007
ACM
14 years 5 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar