Sciweavers

DATE
2008
IEEE
161views Hardware» more  DATE 2008»
13 years 11 months ago
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression
Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, fo...
Bao Liu
SLIP
2009
ACM
13 years 11 months ago
Closed-form solution for timing analysis of process variations on SWCNT interconnect
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
Peng Sun, Rong Luo
ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Variability-aware robust design space exploration of chip multiprocessor architectures
Abstract— In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufactu...
Gianluca Palermo, Cristina Silvano, Vittorio Zacca...
ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou
ASPDAC
2009
ACM
155views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Variation-aware resource sharing and binding in behavioral synthesis
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
Feng Wang 0004, Yuan Xie, Andres Takach
ISPD
2010
ACM
205views Hardware» more  ISPD 2010»
13 years 11 months ago
Total sensitivity based dfm optimization of standard library cells
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
14 years 1 months ago
FPGA device and architecture evaluation considering process variations
Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and withindie va...
Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
14 years 5 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...
DAC
2006
ACM
14 years 5 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu

Publication
576views
15 years 4 months ago
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
Brendan Hargreaves, Henrik Hult, Sherief Reda