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TVLSI
2008
133views more  TVLSI 2008»
12 years 1 months ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty
VTS
2000
IEEE
99views Hardware» more  VTS 2000»
12 years 6 months ago
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
Abhijit Jas, Bahram Pouya, Nur A. Touba
VTS
2003
IEEE
122views Hardware» more  VTS 2003»
12 years 7 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
ITC
2003
IEEE
112views Hardware» more  ITC 2003»
12 years 7 months ago
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault
Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed as well. Unlike the previous scan chain dia...
Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-...
ITC
2003
IEEE
138views Hardware» more  ITC 2003»
12 years 7 months ago
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
Yannick Bonhomme, Patrick Girard, Loïs Guille...
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
12 years 8 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
VTS
2007
IEEE
79views Hardware» more  VTS 2007»
12 years 8 months ago
Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression
A methodology is presented for improving the amount of compression achieved by continuous-flow decompressors by using multiple ratios of scan chains to tester channels (i.e., expa...
Richard Putman, Nur A. Touba
DATE
2007
IEEE
56views Hardware» more  DATE 2007»
12 years 8 months ago
Unknown blocking scheme for low control data volume and high observability
This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and a...
Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar
DELTA
2008
IEEE
12 years 8 months ago
Adaptive Diagnostic Pattern Generation for Scan Chains
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...
Fei Wang, Yu Hu, Xiaowei Li
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
12 years 10 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
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