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    EURODAC
    1995
    IEEE
    314views VHDL» more  EURODAC 1995»
    Procedure exlining: a new system-level specification transformation
    15 years 9 months ago
    Procedure exlining: a new system-level specification transformation
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    Frank Vahid
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    EURODAC
    1995
    IEEE
    293views VHDL» more  EURODAC 1995»
    Functional-level analog macromodeling with piecewise linear signals
    15 years 9 months ago
    Functional-level analog macromodeling with piecewise linear signals
    Download  www.cs.york.ac.uk
    Jerzy Dabrowski
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    EURODAC
    1995
    IEEE
    294views VHDL» more  EURODAC 1995»
    A classification of design steps and their verification
    15 years 9 months ago
    A classification of design steps and their verification
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    Wolfgang Ecker
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    EURODAC
    1995
    IEEE
    162views VHDL» more  EURODAC 1995»
    ODE: output direct state machine encoding
    15 years 9 months ago
    ODE: output direct state machine encoding
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    A somewhat novel approach is presented for determining FSM state codes. Instead of producing an assignment designed to minimise the overall logic of the machine, all Moore outputs...
    J. Forrest
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    EURODAC
    1995
    IEEE
    182views VHDL» more  EURODAC 1995»
    Delay modelling improvement for low voltage applications
    15 years 9 months ago
    Delay modelling improvement for low voltage applications
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    Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
    Jean Michel Daga, Michel Robert, Daniel Auvergne
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