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    153
    Voted
    ISLPED
    1995
    ACM
    129views Hardware» more  ISLPED 1995»
    CMOS dynamic power estimation based on collapsible current source transistor modeling
    15 years 3 months ago
    CMOS dynamic power estimation based on collapsible current source transistor modeling
    Download  www.cecs.uci.edu
    When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
    Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Pet...
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    148
    Voted
    MICRO
    1995
    IEEE
    217views Hardware» more  MICRO 1995»
    Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
    15 years 3 months ago
    Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
    Download  www.cs.virginia.edu
    Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
    Jack W. Davidson, Sanjay Jinturkar
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    146
    Voted
    ISCA
    1995
    IEEE
    147views Hardware» more  ISCA 1995»
    Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
    15 years 3 months ago
    Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
    Download  ftp.cs.wisc.edu
    This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
    Alvin R. Lebeck, David A. Wood
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    ASPDAC
    1995
    ACM
    85views Hardware» more  ASPDAC 1995»
    A robust min-cut improvement algorithm based on dynamic look-ahead weighting
    15 years 4 months ago
    A robust min-cut improvement algorithm based on dynamic look-ahead weighting
    Download  www.cecs.uci.edu
    Katsunori Tani
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    ITC
    1995
    IEEE
    124views Hardware» more  ITC 1995»
    An Experimental Chip to Evaluate Test Techniques: Experiment Results
    15 years 3 months ago
    An Experimental Chip to Evaluate Test Techniques: Experiment Results
    Download  www-crc.stanford.edu
    This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and tes...
    Siyad C. Ma, Piero Franco, Edward J. McCluskey
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