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FCCM
2003
IEEE
210views VLSI» more  FCCM 2003»
15 years 6 months ago
Compact FPGA-based True and Pseudo Random Number Generators
Two FPGA based implementations of random number generators intended for embedded cryptographic applications are presented. The first is a true random number generator (TRNG) whic...
Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong
FCCM
2003
IEEE
185views VLSI» more  FCCM 2003»
15 years 6 months ago
Implementation of a Content-Scanning Module for an Internet Firewall
A module has been implemented in Field Programmable Gate Array (FPGA) hardware that scans the content of Internet packets at Gigabit/second rates. All of the packet processing ope...
James Moscola, John W. Lockwood, Ronald Prescott L...
FCCM
2003
IEEE
168views VLSI» more  FCCM 2003»
15 years 6 months ago
A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons
A second generation of an embedded input device for kinetically challenged persons is presented. The new system can detect O(n2 ) free motions in space with O(n) hardware, and has...
Kyprianos Papademetriou, Apostolos Dollas, Stamati...
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
15 years 6 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
15 years 6 months ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit
VLSI
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