GLVLSI
15 years 6 months ago
2003 IEEE 
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
GLVLSI
15 years 6 months ago
2003 IEEE 
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
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GLVLSI
15 years 6 months ago
2003 IEEE
A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flas...
GLVLSI
15 years 6 months ago
2003 IEEE
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain ...
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VLSI