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ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
15 years 6 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ISVLSI
2003
IEEE
147views VLSI» more  ISVLSI 2003»
15 years 6 months ago
Automated Dynamic Memory Data Type Implementation Exploration and Optimization
The behavior of many algorithms is heavily determined by the input data. Furthermore, this often means that multiple and completely different execution paths can be followed, also...
Marc Leeman, Chantal Ykman-Couvreur, David Atienza...
ISVLSI
2003
IEEE
138views VLSI» more  ISVLSI 2003»
15 years 6 months ago
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory
The need for small, high speed, low power computers as the end of Moore’s law approaches is driving research into nanotechnology. These novel devices have significantly differe...
Sarah E. Frost, Arun Rodrigues, Charles A. Giefer,...
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
15 years 6 months ago
Reconfigurable Fast Memory Management System Design for Application Specific Processors
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...
S. Kagan Agun, J. Morris Chang
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
15 years 6 months ago
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
In this paper, we discuss the possibility of achieving onchip fault-tolerant communication based on a new communication paradigm called stochastic communication. Specifically, for...
Radu Marculescu
VLSI
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