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118
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WMPI
2004
ACM
15 years 2 months ago
A compressed memory hierarchy using an indirect index cache
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
Erik G. Hallnor, Steven K. Reinhardt
DAC
2004
ACM
15 years 9 months ago
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding
This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption using the computational workload decomposition. Th...
Kihwan Choi, Ramakrishna Soma, Massoud Pedram
APCSAC
2004
IEEE
15 years 18 days ago
Validating Word-Oriented Processors for Bit and Multi-word Operations
We examine secure computing paradigms to identify any new architectural challenges for future general-purpose processors. Some essential security functions can be provided by diffe...
Ruby B. Lee, Xiao Yang, Zhijie Shi
DAC
2004
ACM
15 years 9 months ago
Fast statistical timing analysis handling arbitrary delay correlations
CT An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire ...
Michael Orshansky, Arnab Bandyopadhyay
WMPI
2004
ACM
15 years 2 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
Computer Architecture
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