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VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
16 years 10 days ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
16 years 10 days ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
15 years 3 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
DFT
2004
IEEE
134views VLSI» more  DFT 2004»
15 years 3 months ago
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
Defect tolerance is an extremely important aspect in nano-scale electronics as the bottom-up selfassembly fabrication process results in a significantly higher defect density comp...
Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lomb...
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
15 years 3 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
VLSI
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