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223
Voted
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
16 years 7 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
15 years 10 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
16 years 7 months ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...
FCCM
2004
IEEE
129views VLSI» more  FCCM 2004»
15 years 10 months ago
Design Patterns for Reconfigurable Computing
It is valuable to identify and catalog design patterns for reconfigurable computing. These design patterns are canonical solutions to common and recurring design challenges which ...
André DeHon, Joshua Adams, Michael DeLorimi...
214
Voted
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
16 years 7 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
VLSI
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