Sciweavers

CHARME
2005
Springer
176views Hardware» more  CHARME 2005»
15 years 2 months ago
An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment
Abstract. Model checking is a formal technique for automatically verifying that a finite-state model satisfies a temporal property. In model checking, generally Binary Decision D...
Nina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P...
CHARME
2005
Springer
170views Hardware» more  CHARME 2005»
15 years 2 months ago
Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification
Sudhindra Pandav, Konrad Slind, Ganesh Gopalakrish...
CHARME
2005
Springer
145views Hardware» more  CHARME 2005»
14 years 11 months ago
Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies
Abstract. Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present sev...
Jason Baumgartner, Hari Mony
CHARME
2005
Springer
143views Hardware» more  CHARME 2005»
15 years 2 months ago
Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning
Abstract. We propose a new saturation-based symbolic state-space generation algorithm for finite discrete-state systems. Based on the structure of the high-level model specificat...
Gianfranco Ciardo, Andy Jinqing Yu
CHARME
2005
Springer
136views Hardware» more  CHARME 2005»
15 years 2 months ago
Acceleration of SAT-Based Iterative Property Checking
Today, verification is becoming the dominating factor for successful circuit designs. In this context formal verification techniques allow to prove the correctness of a circuit ...
Daniel Große, Rolf Drechsler
Hardware
Top of PageReset Settings