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ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
15 years 2 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
ISCA
2005
IEEE
172views Hardware» more  ISCA 2005»
15 years 2 months ago
An Ultra Low Power System Architecture for Sensor Network Applications
Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networ...
Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu...
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
15 years 2 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu
ISCA
2005
IEEE
162views Hardware» more  ISCA 2005»
15 years 2 months ago
Mitigating Amdahl's Law through EPI Throttling
Murali Annavaram, Ed Grochowski, John Paul Shen
ISCA
2005
IEEE
154views Hardware» more  ISCA 2005»
15 years 2 months ago
Temporal Streaming of Shared Memory
Coherent read misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. We propose Tempor...
Thomas F. Wenisch, Stephen Somogyi, Nikolaos Harda...
Hardware
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