Sciweavers

DSN
2007
IEEE
15 years 6 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
DSN
2007
IEEE
15 years 6 months ago
Dynamic Fault Tree Analysis Using Input/Output Interactive Markov Chains
Dynamic Fault Trees (DFT) extend standard fault trees by allowing the modeling of complex system components’ behaviors and interactions. Being a high level model and easy to use...
Hichem Boudali, Pepijn Crouzen, Mariëlle Stoe...
DSN
2007
IEEE
15 years 6 months ago
Web Services Wind Tunnel: On Performance Testing Large-Scale Stateful Web Services
New versions of existing large-scale web services such as Passport.com© have to go through rigorous performance evaluations in order to ensure a high degree of availability. Perf...
Marcelo De Barros, Jing Shiau, Chen Shang, Kenton ...
DSN
2007
IEEE
15 years 6 months ago
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
Computer Networks
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