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FCCM
2007
IEEE
485views VLSI» more  FCCM 2007»
15 years 3 months ago
Low-Cost Stereo Vision on an FPGA
We present a low-cost stereo vision implementation suitable for use in autonomous vehicle applications and designed with agricultural applications in mind. This implementation uti...
Chris Murphy, Daniel Lindquist, Ann Marie Rynning,...
GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
15 years 6 months ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...
ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
15 years 6 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
16 years 12 days ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...
VLSI
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