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ASAP
2008
IEEE
199views Hardware» more  ASAP 2008»
15 years 5 months ago
An efficient method for evaluating polynomial and rational function approximations
In this paper we extend the domain of applicability of the E-method [7, 8], as a hardware-oriented method for evaluating elementary functions using polynomial and rational functio...
Nicolas Brisebarre, Sylvain Chevillard, Milos D. E...
ASAP
2008
IEEE
186views Hardware» more  ASAP 2008»
15 years 10 months ago
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs
RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-thro...
Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberla...
ASAP
2008
IEEE
182views Hardware» more  ASAP 2008»
15 years 10 months ago
Low-cost implementations of NTRU for pervasive security
NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an alternative to RSA and ECC. This work presents a compact and low power NTRU design ...
Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid V...
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
15 years 10 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
15 years 5 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
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