131
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HPCA
16 years 29 days ago
2009 IEEE 
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
98
Voted
HPCA
16 years 29 days ago
2009 IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
108
Voted
HPCA
16 years 29 days ago
2009 IEEE
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...
121
Voted
HPCA
16 years 29 days ago
2009 IEEE 
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
101
Voted
HPCA
15 years 7 months ago
2009 IEEE 
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
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Distributed And Parallel Computing