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ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
9 years 1 months ago
Multi-metric and multi-entity characterization of applications for early system design exploration
— At system level, intensively analyzing the system application will produce a variety of useful characteristics and provide designers valuable exploration indications. In this p...
Lukai Cai, Andreas Gerstlauer, Daniel Gajski
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
9 years 1 months ago
Wire-driven microarchitectural design space exploration
— In this paper, we propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. ...
Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram,...
IPPS
2006
IEEE
9 years 2 months ago
Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Pr...
Riad Ben Mouhoub, Omar Hammami
CODES
2006
IEEE
9 years 2 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
CODES
2006
IEEE
9 years 2 months ago
A formal approach to robustness maximization of complex heterogeneous embedded systems
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...
Arne Hamann, Razvan Racu, Rolf Ernst
SIES
2007
IEEE
9 years 2 months ago
Design Space Exploration with Evolutionary Multi-Objective Optimisation
— High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high nthesis are two-fold. At first the level of abstraction is r...
Martin Holzer 0002, Bastian Knerr, Markus Rupp
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
9 years 2 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
DSD
2007
IEEE
116views Hardware» more  DSD 2007»
9 years 2 months ago
Evaluating the Model Accuracy in Automated Design Space Exploration
Design space exploration is used to shorten the design time of System-on-Chips (SoCs). The models used in the exploration need to be both accurate and fast to simulate. This paper...
Kalle Holma, Mikko Setälä, Erno Salminen...
CODES
2007
IEEE
9 years 2 months ago
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs
In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology ...
Mark Thompson, Hristo Nikolov, Todor Stefanov, And...
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
9 years 2 months ago
System Level Design Space Exploration for Multiprocessor System on Chip
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods...
Issam Maalej, Guy Gogniat, Jean Luc Philippe, Moha...
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