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ISCAS
2007
IEEE
167views Hardware» more  ISCAS 2007»
13 years 11 months ago
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
Afshin Nourivand, Chunyan Wang, M. Omair Ahmad
ISCAS
2007
IEEE
92views Hardware» more  ISCAS 2007»
13 years 11 months ago
A Study on Impact of Leakage Current on Dynamic Power
— Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now beco...
Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu
IPCCC
2007
IEEE
13 years 11 months ago
Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization
Leakage power is a major concern in current microarchitectures as it is increasing exponentially with decreasing transistor feature sizes. In this paper, we present a technique ca...
Santosh Talli, Ram Srinivasan, Jeanine Cook
GLVLSI
2007
IEEE
114views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Design of mixed gates for leakage reduction
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
Frank Sill, Jiaxi You, Dirk Timmermann
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
13 years 11 months ago
Microarchitecture floorplanning for sub-threshold leakage reduction
Lateral heat conduction between modules affects the temperature profile of a floorplan, affecting the leakage power of individual blocks which increasingly is becoming a larger ...
Hushrav Mogal, Kia Bazargan
DATE
2007
IEEE
134views Hardware» more  DATE 2007»
13 years 11 months ago
Accurate temperature-dependent integrated circuit leakage power estimation is easy
— It has been the conventional assumption that, due to the superlinear dependence of leakage power consumption on temperature, and widely varying on-chip temperature profiles, a...
Yongpan Liu, Robert P. Dick, Li Shang, Huazhong Ya...
NOCS
2008
IEEE
13 years 11 months ago
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang,...
ISQED
2008
IEEE
150views Hardware» more  ISQED 2008»
13 years 11 months ago
Fundamental Data Retention Limits in SRAM Standby Experimental Results
SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is ofte...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
13 years 11 months ago
"Green" micro-architecture and circuit co-design for ternary content addressable memory
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hw...
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
13 years 11 months ago
A Scalable Algorithmic Framework for Row-Based Power-Gating
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...