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DATE
2008
IEEE
128views Hardware» more  DATE 2008»
13 years 11 months ago
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution
This paper presents a method of dynamic voltage scaling (DVS) that tackles both switching and leakage power with combined Vdd/Vbs scaling and gives minimum average energy consumpt...
Sungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung ...
ISLPED
2009
ACM
118views Hardware» more  ISLPED 2009»
13 years 11 months ago
Serial sub-threshold circuits for ultra-low-power systems
This paper explores the use of serial circuits for ultra-low-power sub-threshold systems. A serial system leads to a smaller design and higher utilization, yielding 40% active ene...
Sudhanshu Khanna, Benton H. Calhoun
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
13 years 11 months ago
Gate replacement techniques for simultaneous leakage and aging optimization
—1As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, r...
Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao,...
ISQED
2009
IEEE
124views Hardware» more  ISQED 2009»
13 years 11 months ago
Revisiting the linear programming framework for leakage power vs. performance optimization
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
Kwangok Jeong, Andrew B. Kahng, Hailong Yao
ISQED
2010
IEEE
151views Hardware» more  ISQED 2010»
13 years 11 months ago
Leakage temperature dependency modeling in system level analysis
Abstract— As the semiconductor technology continues its marching toward the deep sub-micron domain, the strong relation between leakage current and temperature becomes critical i...
Huang Huang, Gang Quan, Jeffrey Fan
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
13 years 11 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 1 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
14 years 1 months ago
Thermal-Aware Clustered Microarchitectures
As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it ...
Pedro Chaparro, José González, Anton...
ICCD
2008
IEEE
118views Hardware» more  ICCD 2008»
14 years 1 months ago
Adaptive techniques for leakage power management in L2 cache peripheral circuits
— Recent studies indicate that a considerable amount of an L2 cache leakage power is dissipated in its peripheral circuits, e.g., decoders, word-lines and I/O drivers. In additio...
Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc...
VLSID
2002
IEEE
92views VLSI» more  VLSID 2002»
14 years 5 months ago
Low Power Solution for Wireless Applications
Low standby power dissipation is the primary need for most of the wireless applications for prolonged battery life. Traditionally ASIC solutions currently address either high densi...
Sornavalli Ramanathan, Rituparna Mandal