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RTSS
1994
IEEE
15 years 5 months ago
Bounding Worst-Case Instruction Cache Performance
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
Robert D. Arnold, Frank Mueller, David B. Whalley,...
HYBRID
1994
Springer
15 years 5 months ago
DEVS Framework for Modelling, Simulation, Analysis, and Design of Hybrid Systems
We make the case that Discrete Event System Speci cation DEVS is a universal formalismfor discrete event dynamical systems DEDS. DEVS o ers an expressive framework for modelling, ...
Bernard P. Zeigler, Hae Sang Song, Tag Gon Kim, He...
RTSS
1994
IEEE
15 years 5 months ago
On-Line Scheduling to Maximize Task Completions
The problem of uniprocessor scheduling under conditions of overload is investigated. The system objective is to maximzze the number of tasks that complete by their deadlines. For ...
Sanjoy K. Baruah, Jayant R. Haritsa, Nitin Sharma
RTSS
1994
IEEE
15 years 5 months ago
Timeliness via Speculation for Real-Time Databases
Various concurrency control algorithms di er in the time when con icts are detected, and in the way they are resolved. In that respect, the Pessimistic and Optimistic Concurrency ...
Azer Bestavros, Spyridon Braoudakis
HYBRID
1994
Springer
15 years 5 months ago
Symbolic Controller Synthesis for Discrete and Timed Systems
This paper presents algorithms for the symbolic synthesis of discrete and real-time controllers. At the semantic level the controller is synthesized by nding a winning strategy for...
Eugene Asarin, Oded Maler, Amir Pnueli
Control Systems
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