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RTSS
1994
IEEE
15 years 4 months ago
Bounding Worst-Case Instruction Cache Performance
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
Robert D. Arnold, Frank Mueller, David B. Whalley,...
110
Voted
HYBRID
1994
Springer
15 years 4 months ago
DEVS Framework for Modelling, Simulation, Analysis, and Design of Hybrid Systems
We make the case that Discrete Event System Speci cation DEVS is a universal formalismfor discrete event dynamical systems DEDS. DEVS o ers an expressive framework for modelling, ...
Bernard P. Zeigler, Hae Sang Song, Tag Gon Kim, He...
RTSS
1994
IEEE
15 years 4 months ago
On-Line Scheduling to Maximize Task Completions
The problem of uniprocessor scheduling under conditions of overload is investigated. The system objective is to maximzze the number of tasks that complete by their deadlines. For ...
Sanjoy K. Baruah, Jayant R. Haritsa, Nitin Sharma
99
Voted
HYBRID
1994
Springer
15 years 4 months ago
Symbolic Controller Synthesis for Discrete and Timed Systems
This paper presents algorithms for the symbolic synthesis of discrete and real-time controllers. At the semantic level the controller is synthesized by nding a winning strategy for...
Eugene Asarin, Oded Maler, Amir Pnueli
RTSS
1994
IEEE
15 years 4 months ago
Guaranteeing End-to-End Timing Constraints by Calibrating Intermediate Processes
This paper presents a comprehensive design methodology for guaranteeing end-to-end requirements of real-time systems. Applications are structured as a set of process components co...
Richard Gerber, Seongsoo Hong, Manas Saksena
Control Systems
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