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    168
    Voted
    DFT
    1994
    IEEE
    121views VLSI» more  DFT 1994»
    Reconfiguration in 3D Meshes
    15 years 11 months ago
    Reconfiguration in 3D Meshes
    Download  www.cs.pitt.edu
    The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
    Anuj Chandra, Rami G. Melhem
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    VLSID
    1994
    IEEE
    124views VLSI» more  VLSID 1994»
    ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
    15 years 11 months ago
    ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
    Download  www.cs.kent.edu
    In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
    Samit Chaudhuri, Robert A. Walker
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    VLSID
    1994
    IEEE
    108views VLSI» more  VLSID 1994»
    A New Genetic Algorithm for the Channel Routing Problem
    15 years 10 months ago
    A New Genetic Algorithm for the Channel Routing Problem
    Download  www.cs.ou.edu
    Jens Lienig, Krishnaiyan Thulasiraman
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    158
    Voted
    VLSID
    1994
    IEEE
    151views VLSI» more  VLSID 1994»
    A CORDIC Based Programmable DXT Processor Array
    15 years 11 months ago
    A CORDIC Based Programmable DXT Processor Array
    Download  eprints.iisc.ernet.in
    A CORDIC based processor array which can be programmed by switch settings to compute the Discrete Hariley, Cosine or Sine lhnsforms or their inverses is described. Through a novel...
    V. K. Anuradha, V. Visvanathan
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    149
    Voted
    DFT
    1994
    IEEE
    157views VLSI» more  DFT 1994»
    An Approach to the Development of a IDDQ Testable Cell Library
    15 years 11 months ago
    An Approach to the Development of a IDDQ Testable Cell Library
    Download  pmos.upc.es
    C. Ferrer, D. Dateo, J. Oliver, Antonio Rubio, M. ...
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