194
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DFT
15 years 11 months ago
1994 IEEE 
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
189
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VLSID
15 years 11 months ago
1994 IEEE
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
176
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VLSID
15 years 11 months ago
1994 IEEE 
A CORDIC based processor array which can be programmed by switch settings to compute the Discrete Hariley, Cosine or Sine lhnsforms or their inverses is described. Through a novel...
165
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VLSID
15 years 11 months ago
1994 IEEE 
: This paper describes techniques for energy efficient implementation of programmable computation. consumption in programmable computation can be substantiallvlowered with nolossin...
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VLSI