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    EURODAC
    1994
    IEEE
    377views VHDL» more  EURODAC 1994»
    VHDL switch level fault simulation
    15 years 8 months ago
    VHDL switch level fault simulation
    Download  www.cecs.uci.edu
    Christopher A. Ryan, Joseph G. Tront
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    EURODAC
    1994
    IEEE
    272views VHDL» more  EURODAC 1994»
    A transformation for integrating VHDL behavioral specification with synthesis and software generation
    15 years 8 months ago
    A transformation for integrating VHDL behavioral specification with synthesis and software generation
    Download  www.cecs.uci.edu
    Frank Vahid, Daniel D. Gajski, Sanjiv Narayan
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    EURODAC
    1994
    IEEE
    148views VHDL» more  EURODAC 1994»
    System-Level Modeling and Verification: a Comprehensive Design Methodology
    15 years 7 months ago
    System-Level Modeling and Verification: a Comprehensive Design Methodology
    Download  www.cad.polito.it
    Paolo Camurati, Fulvio Corno, Paolo Prinetto, Cath...
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    EURODAC
    1994
    IEEE
    149views VHDL» more  EURODAC 1994»
    A flexible access control mechanism for CAD frameworks
    15 years 7 months ago
    A flexible access control mechanism for CAD frameworks
    Download  www.cs.york.ac.uk
    A. J. van der Hoeven, K. Olav ten Bosch, Rene van ...
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    EURODAC
    1994
    IEEE
    148views VHDL» more  EURODAC 1994»
    BiTeS: a BDD based test pattern generator for strong robust path delay faults
    15 years 8 months ago
    BiTeS: a BDD based test pattern generator for strong robust path delay faults
    Download  www.cecs.uci.edu
    This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
    Rolf Drechsler
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