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    2007
    IEEE
    161views Hardware» more  ASYNC 2007»
    Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
    15 years 10 months ago
    Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
    Download  conferences.computer.org
    Mark B. Josephs
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    138
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    ASYNC
    2007
    IEEE
    154views Hardware» more  ASYNC 2007»
    Design of a High-Speed Asynchronous Turbo Decoder
    15 years 10 months ago
    Design of a High-Speed Asynchronous Turbo Decoder
    Download  jungfrau.usc.edu
    This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
    Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...
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    ASYNC
    2007
    IEEE
    146views Hardware» more  ASYNC 2007»
    Notes On Pulse Signaling
    15 years 10 months ago
    Notes On Pulse Signaling
    Download  labs.oracle.com
    This paper reports results of a study on pulse signaling. In pulse signaling, components communicate by means of pulses instead of voltage transitions. The functionality of the co...
    Jo C. Ebergen, Steve Furber, Arash Saifhashemi
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    ASYNC
    2007
    IEEE
    143views Hardware» more  ASYNC 2007»
    Demystifying Data-Driven and Pausible Clocking Schemes
    15 years 10 months ago
    Demystifying Data-Driven and Pausible Clocking Schemes
    Download  www.cl.cam.ac.uk
    Robert D. Mullins, Simon W. Moore
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    ASYNC
    2007
    IEEE
    132views Hardware» more  ASYNC 2007»
    Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
    15 years 10 months ago
    Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
    Download  www.cs.cmu.edu
    Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
    Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
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