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109
Voted
ICCD
2007
IEEE
746views Hardware» more  ICCD 2007»
15 years 9 months ago
Hardware design of a Binary Integer Decimal-based floating-point adder
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...
Charles Tsen, Sonia Gonzalez-Navarro, Michael J. S...
98
Voted
ICCD
2007
IEEE
322views Hardware» more  ICCD 2007»
15 years 9 months ago
Voltage drop reduction for on-chip power delivery considering leakage current variations
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
ICCD
2007
IEEE
245views Hardware» more  ICCD 2007»
15 years 9 months ago
FPGA global routing architecture optimization using a multicommodity flow approach
Low energy and small switch area usage are two of the important design objectives in FPGA global routing architecture design. This paper presents an improved MCF model based CAD ...
Yuanfang Hu, Yi Zhu, Michael Bedford Taylor, Chung...
ICCD
2007
IEEE
225views Hardware» more  ICCD 2007»
15 years 9 months ago
Fine grain 3D integration for microarchitecture design through cube packing exploration
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm...
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
15 years 9 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
Hardware
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