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ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
15 years 7 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
91
Voted
ISCA
2009
IEEE
276views Hardware» more  ISCA 2009»
15 years 7 months ago
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
Yuejian Xie, Gabriel H. Loh
112
Voted
ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
15 years 7 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
92
Voted
ISCA
2009
IEEE
230views Hardware» more  ISCA 2009»
15 years 7 months ago
Architecting phase change memory as a scalable dram alternative
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM)...
Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burg...
90
Voted
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
15 years 7 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...
Hardware
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