Sciweavers

VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 3 months ago
Efficient Macromodeling for On-Chip Interconnects
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
Qinwei Xu, Pinaki Mazumder
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
14 years 3 months ago
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun...
VLSID
2002
IEEE
99views VLSI» more  VLSID 2002»
14 years 3 months ago
Input Space Adaptive Embedded Software Synthesis
This paper presents a novel technique, called input space adaptive software synthesis, for the energy and performance optimization of embedded software. The proposed technique is ...
Weidong Wang, Anand Raghunathan, Ganesh Lakshminar...
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
14 years 3 months ago
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
VLSID
2002
IEEE
78views VLSI» more  VLSID 2002»
14 years 3 months ago
Optimization of Test Accesses with a Combined BIST and External Test Scheme
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
Makoto Sugihara, Hiroto Yasuura
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 3 months ago
A Design of Analog C-Matrix Circuits Used for Signal/Data Processing
Various calculation of matrices and vectors has been used in many digital signal processing systems. Although the calculation simply repeats multiplication and addition, the reite...
Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yo...
VLSID
2002
IEEE
124views VLSI» more  VLSID 2002»
14 years 3 months ago
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods
We present an efficient implementation of an approximate balanced truncation model reduction technique for general large-scale RLC systems, described by a statespace model where t...
Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
VLSID
2002
IEEE
60views VLSI» more  VLSID 2002»
14 years 3 months ago
Transistor Flaring in Deep Submicron-Design Considerations
Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes ...
Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R....
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 3 months ago
Architecture and Design of a High Performance SRAM for SOC Design
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...
Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka P...
VLSID
2002
IEEE
135views VLSI» more  VLSID 2002»
14 years 3 months ago
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
Rupesh S. Shelar, Sachin S. Sapatnekar