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ICCD
2004
IEEE
172views Hardware» more  ICCD 2004»
16 years 3 months ago
A Signal Integrity Test Bed for PCB Buses
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
Jihong Ren, Mark R. Greenstreet
198
Voted
ICCD
2004
IEEE
137views Hardware» more  ICCD 2004»
16 years 3 months ago
Comparative Study of Strategies for Formal Verification of High-Level Processors
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
Miroslav N. Velev
193
Voted
ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
16 years 3 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
16 years 3 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...
ICCD
2004
IEEE
97views Hardware» more  ICCD 2004»
16 years 3 months ago
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
John Lach, Jason Brandon, Kevin Skadron
Hardware
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