101
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ICCD
15 years 7 months ago
2004 IEEE 
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
ICCD
15 years 7 months ago
2004 IEEE
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
ICCD
15 years 7 months ago
2004 IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
ICCD
15 years 7 months ago
2004 IEEE
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
ICCD
15 years 7 months ago
2004 IEEE
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
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