ICCD
15 years 5 months ago
2004 IEEE 
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
ICCD
15 years 5 months ago
2004 IEEE
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
ICCD
15 years 5 months ago
2004 IEEE
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
ICCD
15 years 5 months ago
2004 IEEE
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
ICCD
15 years 5 months ago
2004 IEEE
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
|
Hardware