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ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
15 years 2 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ISPD
2004
ACM
189views Hardware» more  ISPD 2004»
15 years 2 months ago
Almost optimum placement legalization by minimum cost flow and dynamic programming
VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, i...
Ulrich Brenner, Anna Pauli, Jens Vygen
ISPD
2004
ACM
161views Hardware» more  ISPD 2004»
15 years 2 months ago
Early-stage power grid analysis for uncertain working modes
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance ...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
ISPD
2004
ACM
97views Hardware» more  ISPD 2004»
15 years 2 months ago
Implementation and extensibility of an analytic placer
Automated cell placement is a critical problem in VLSI physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently rec...
Andrew B. Kahng, Qinke Wang
ISPD
2004
ACM
134views Hardware» more  ISPD 2004»
15 years 2 months ago
Performance-driven register insertion in placement
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
Dennis K. Y. Tong, Evangeline F. Y. Young
Hardware
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