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GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
7 years 7 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
7 years 7 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
FCCM
2011
IEEE
311views VLSI» more  FCCM 2011»
7 years 7 months ago
String Matching in Hardware Using the FM-Index
—String matching is a ubiquitous problem that arises in a wide range of applications in computing, e.g., packet routing, intrusion detection, web querying, and genome analysis. D...
Edward Fernandez, Walid Najjar, Stefano Lonardi
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
7 years 7 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
7 years 7 months ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
8 years 1 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
8 years 1 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
FCCM
2009
IEEE
139views VLSI» more  FCCM 2009»
8 years 1 months ago
Memory-Efficient Pipelined Architecture for Large-Scale String Matching
We propose a pipelined field-merge architecture for memory-efficient and high-throughput large-scale string matching (LSSM). Our proposed architecture partitions the (8-bit) charac...
Yi-Hua Edward Yang, Viktor K. Prasanna
FCCM
2009
IEEE
170views VLSI» more  FCCM 2009»
8 years 1 months ago
Generic Software Framework for Adaptive Applications on FPGAs
Adaptive systems are set to become more mainstream, as numerous practical applications in the communications domain emerge. FPGAs offer an ideal implementation platform, combining...
Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda...
VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
8 years 1 months ago
Synchronized Generation of Directed Tests Using Satisfiability Solving
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
Xiaoke Qin, Mingsong Chen, Prabhat Mishra
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