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DFT
2008
IEEE
149views VLSI» more  DFT 2008»
8 years 5 months ago
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?
Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various count...
Francesco Regazzoni, Thomas Eisenbarth, Luca Breve...
DFT
2008
IEEE
151views VLSI» more  DFT 2008»
8 years 5 months ago
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris...
DFT
2008
IEEE
182views VLSI» more  DFT 2008»
8 years 5 months ago
Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis
This paper addresses a new threat to the security of integrated circuits (ICs). The migration of IC fabrication to untrusted foundries has made ICs vulnerable to malicious alterat...
Xiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoo...
GLVLSI
2007
IEEE
142views VLSI» more  GLVLSI 2007»
8 years 5 months ago
Three-valued automated reasoning on analog properties
Raffaella Gentilini, Klaus Schneider, Alexander Dr...
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
8 years 5 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
GLVLSI
2007
IEEE
153views VLSI» more  GLVLSI 2007»
8 years 5 months ago
Address generation for nanowire decoders
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
Jia Wang, Ming-Yang Kao, Hai Zhou
FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
8 years 5 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
DFT
2005
IEEE
102views VLSI» more  DFT 2005»
8 years 5 months ago
Using Statistical Transformations to Improve Compression for Linear Decompressors
Linear decompressors are the dominant methodology used in commercial test data compression tools. However, they are generally not able to exploit correlations in the test data, an...
Samuel I. Ward, Chris Schattauer, Nur A. Touba
DFT
2005
IEEE
132views VLSI» more  DFT 2005»
8 years 5 months ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
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