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    125
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    VLSID
    1995
    IEEE
    113views VLSI» more  VLSID 1995»
    VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
    15 years 6 months ago
    VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
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    Luca Penzo, Donatella Sciuto, Cristina Silvano
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    108
    Voted
    VLSID
    1995
    IEEE
    112views VLSI» more  VLSID 1995»
    An efficient automatic test generation system for path delay faults in combinational circuits
    15 years 6 months ago
    An efficient automatic test generation system for path delay faults in combinational circuits
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    Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
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    102
    Voted
    VLSID
    1995
    IEEE
    104views VLSI» more  VLSID 1995»
    A VLSI architecture for the computation of NURBS patches
    15 years 6 months ago
    A VLSI architecture for the computation of NURBS patches
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    Meenakshisundaram Gopi, Swami Manohar
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    98
    Voted
    VLSID
    1995
    IEEE
    109views VLSI» more  VLSID 1995»
    Logic minimization based approach for compressing image data
    15 years 6 months ago
    Logic minimization based approach for compressing image data
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    Jacob Augustine, Wen Feng, James Jacob
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    94
    Voted
    VLSID
    1995
    IEEE
    97views VLSI» more  VLSID 1995»
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
    15 years 6 months ago
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
    Download  www1.cs.columbia.edu
    In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free
    Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
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