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DFT
2007
IEEE
152views VLSI» more  DFT 2007»
15 years 4 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
Cristiana Bolchini, Antonio Miele, Marco D. Santam...
DFT
2007
IEEE
142views VLSI» more  DFT 2007»
15 years 6 months ago
Quantitative Analysis of In-Field Defects in Image Sensor Arrays
Growth of pixel density and sensor array size increases the likelihood of developing in-field pixel defects. An ongoing study on defect development in imagers has now provided us ...
Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israe...
DFT
2007
IEEE
141views VLSI» more  DFT 2007»
15 years 6 months ago
A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects
Solid-state image sensors develop in-field defects in all common environments. Experiments have demonstrated the growth of significant quantities of hot-pixel defects that degrade...
Jozsef Dudas, Michelle L. La Haye, Jenny Leung, Gl...
DFT
2007
IEEE
135views VLSI» more  DFT 2007»
15 years 6 months ago
Fault Secure Encoder and Decoder for Memory Applications
We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry....
Helia Naeimi, André DeHon
DFT
2007
IEEE
123views VLSI» more  DFT 2007»
15 years 6 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
VLSI
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