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ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
15 years 6 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
15 years 6 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...
ISVLSI
2007
IEEE
205views VLSI» more  ISVLSI 2007»
15 years 6 months ago
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
Angan Das, Ranga Vemuri
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
15 years 6 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
ISVLSI
2007
IEEE
194views VLSI» more  ISVLSI 2007»
15 years 6 months ago
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload
Ewerson Carvalho, Ney Laert Vilar Calazans, Fernan...
VLSI
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