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VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
16 years 13 days ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
16 years 13 days ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
VLSID
2007
IEEE
209views VLSI» more  VLSID 2007»
16 years 13 days ago
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
Saraju P. Mohanty, Elias Kougianos
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
16 years 13 days ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
16 years 13 days ago
Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques
Claas Cornelius, Frank Grassert, Siegmar Koppe, Di...
VLSI
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