154
Voted
DFT
15 years 3 months ago
2009 IEEE 
Optimizing the BIST configuration based on the characteristics of the design under test is a complicated and challenging work for test engineers. Since this problem has multiple o...
DFT
15 years 7 months ago
2009 IEEE 
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
DFT
15 years 7 months ago
2009 IEEE 
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
84
Voted
DFT
15 years 7 months ago
2009 IEEE 
Hybrid CMOS/non-CMOS memories, in short hybrid memories, have been lauded as future ultra-capacity data memories. Nonetheless, such memories are going to suffer from high degree o...
94
Voted
DFT
15 years 7 months ago
2009 IEEE 
This paper presents a study of errors that occur in DNA self-assembly using synthesized tile sets for template manufacturing. It is shown that due to the reduced size, aggregates ...
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VLSI