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89
Voted
VLSID
2009
IEEE
223views VLSI» more  VLSID 2009»
16 years 1 months ago
Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies
Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate lea...
Bardia Bozorgzadeh, Ali Afzali-Kusha
100
Voted
VLSID
2009
IEEE
220views VLSI» more  VLSID 2009»
16 years 1 months ago
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (Q...
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi...
VLSID
2009
IEEE
182views VLSI» more  VLSID 2009»
15 years 7 months ago
Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design
Abstract— This paper introduces a fuzzy logic based guidance architecture to a graph grammar framework for automated design of analog circuits. The grammar generates circuit topo...
Angan Das, Ranga Vemuri
142
Voted
VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
16 years 1 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
100
Voted
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 1 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
VLSI
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