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125
Voted
RECONFIG
2009
IEEE
269views VLSI» more  RECONFIG 2009»
15 years 7 months ago
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
Guilherme Guindani, Frederico Ferlini, Jeferson Ol...
79
Voted
RECONFIG
2009
IEEE
188views VLSI» more  RECONFIG 2009»
15 years 7 months ago
Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units
Antoine Trouve, Lovic Gauthier, Takayuki Kando, Be...
96
Voted
RECONFIG
2009
IEEE
182views VLSI» more  RECONFIG 2009»
15 years 7 months ago
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
Siddhartha Datta, Ron Sass
100
Voted
RECONFIG
2009
IEEE
172views VLSI» more  RECONFIG 2009»
15 years 7 months ago
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Abstract—The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customar...
Shivam Bhasin, Jean-Luc Danger, Florent Flament, T...
RECONFIG
2009
IEEE
165views VLSI» more  RECONFIG 2009»
15 years 7 months ago
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
Muhammad Aqeel Wahlah, Kees G. W. Goossens
VLSI
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