154
click to vote
ICCAD
15 years 4 months ago
1994 IEEE 
Interconnectperformance does not scale well into deep submicron dimensions, and the rising number of analog effects erodes tal abstraction necessary for high levels of integration...
132
Voted
ICCAD
15 years 4 months ago
1994 IEEE 
In this paper we present an enhanced design flow model that increases the capabilities of a CAD framework to support design activities on hierarchical multi-view design descriptio...
128
Voted
ICCAD
15 years 4 months ago
1994 IEEE
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
125
click to vote
ICCAD
15 years 4 months ago
1994 IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
125
click to vote
ICCAD
15 years 4 months ago
1994 IEEE
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...
|
Hardware