215
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ITC
15 years 11 months ago
1994 IEEE 
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
179
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ITC
15 years 11 months ago
1994 IEEE 
: The IC test industry has struggled .for more than 30years to establish a test approach that would guarantee a low defect level to the customer. Wepropose a comprehensive strategy...
174
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ITC
15 years 11 months ago
1994 IEEE 
For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavi...
144
Voted
ITC
15 years 11 months ago
1994 IEEE |
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