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FCCM
2006
IEEE
404views VLSI» more  FCCM 2006»
15 years 2 months ago
General Architecture for Hardware Implementation of Genetic Algorithm
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...
FCCM
2006
IEEE
268views VLSI» more  FCCM 2006»
15 years 2 months ago
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
Yousef El-Kurdi, Warren J. Gross, Dennis Giannacop...
VLSID
2006
IEEE
240views VLSI» more  VLSID 2006»
15 years 9 months ago
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal process...
Venkataraman Mahalingam, N. Ranganathan
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 3 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
FCCM
2006
IEEE
201views VLSI» more  FCCM 2006»
15 years 17 days ago
Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers
With advances in reconfigurable hardware, especially field-programmable gate arrays (FPGAs), it has become possible to use reconfigurable hardware to accelerate complex applicatio...
Ronald Scrofano, Maya Gokhale, Frans Trouw, Viktor...
VLSI
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