172
Voted
DFT
15 years 9 months ago
2006 IEEE 
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
150
Voted
DFT
15 years 5 months ago
2006 IEEE 
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
147
Voted
DFT
15 years 9 months ago
2006 IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
142
Voted
DFT
15 years 9 months ago
2006 IEEE
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
139
Voted
DFT
15 years 9 months ago
2006 IEEE
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
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VLSI