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153
Voted
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
15 years 6 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
149
Voted
ISSS
1995
IEEE
115views Hardware» more  ISSS 1995»
15 years 6 months ago
A system level design methodology for the optimization of heterogeneous multiprocessors
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems,...
Markus Schwiegershausen, Peter Pirsch
138
Voted
ISSS
1995
IEEE
83views Hardware» more  ISSS 1995»
15 years 6 months ago
Profiling in the ASP codesign environment
Automation of the Hardware/Software Codesign methodology brings with it the need to develop sophisticated high-level profiling tools. This paper presents a profiling tool which us...
Matthew F. Parkinson, Sri Parameswaran
123
Voted
ISSS
1995
IEEE
104views Hardware» more  ISSS 1995»
15 years 6 months ago
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
One of the key issues in hardware/software{cosynthesis is precise estimation. The usual local estimation techniques are inadequate for globally optimising compilers and synthesis ...
Jörg Henkel, Rolf Ernst
120
Voted
ISSS
1995
IEEE
117views Hardware» more  ISSS 1995»
15 years 6 months ago
Scheduling and resource binding for low power
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
Enric Musoll, Jordi Cortadella
Hardware
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