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148
Voted
MICRO
1995
IEEE
217views Hardware» more  MICRO 1995»
15 years 4 months ago
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
Jack W. Davidson, Sanjay Jinturkar
MICRO
1995
IEEE
125views Hardware» more  MICRO 1995»
15 years 4 months ago
Disjoint eager execution: an optimal form of speculative execution
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
Augustus K. Uht, Vijay Sindagi, Kelley Hall
114
Voted
MICRO
1995
IEEE
108views Hardware» more  MICRO 1995»
15 years 4 months ago
SPAID: software prefetching in pointer- and call-intensive environments
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
Mikko H. Lipasti, William J. Schmidt, Steven R. Ku...
111
Voted
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
15 years 4 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
MICRO
1995
IEEE
81views Hardware» more  MICRO 1995»
15 years 4 months ago
The M-Machine multicomputer
Marco Fillo, Stephen W. Keckler, William J. Dally,...
Hardware
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