146
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ISCA
15 years 4 months ago
1995 IEEE 
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
131
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ISCA
15 years 4 months ago
1995 IEEE 
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
127
Voted
ISCA
15 years 4 months ago
1995 IEEE 
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...
125
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ISCA
15 years 4 months ago
1995 IEEE 
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
118
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ISCA
15 years 4 months ago
1995 IEEE 
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
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