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ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
15 years 6 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
ICCAD
1995
IEEE
180views Hardware» more  ICCAD 1995»
15 years 6 months ago
Design based analog testing by Characteristic Observation Inference
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...
ICCAD
1995
IEEE
90views Hardware» more  ICCAD 1995»
15 years 6 months ago
An optimal algorithm for area minimization of slicing floorplans
The traditional algorithm of Stockmeyer for area minimization of slicing oorplans has time (and space) complexity O(n2 ) in the worst case, or O(nlogn) for balanced slicing. For ...
Weiping Shi
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
15 years 6 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
15 years 6 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
Hardware
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