236
Voted
MICRO
15 years 2 months ago
2006 IEEE 
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
118
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MICRO
15 years 8 months ago
2006 IEEE 
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
142
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MICRO
15 years 2 months ago
2006 IEEE 
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
101
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MICRO
15 years 8 months ago
2006 IEEE
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
126
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MICRO
15 years 8 months ago
2006 IEEE 
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
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Hardware